1. Technical Field to which the Invention Belongs
The present invention relates to a pulse processing circuit which outputs the logical sum of non-overlapping pulses and a frequency multiplier circuit.
2. Prior Art
In a certain frequency multiplier circuit in the prior art, non-overlapping pulses are generated by utilizing the shifts of multiphase clocks, and the logical sum of the non-overlapping pulses is taken, thereby a clock frequency which is N times higher is obtained.
Here, in the prior-art frequency multiplier circuit, a multi-input OR circuit is employed in order to take the logical sum of the non-overlapping pulses.
FIG. 10 is a diagram showing the first example arrangement of a multi-input OR circuit in the prior art. Incidentally, in the example of FIG. 10, a 3-input OR circuit is shown for the sake of brevity.
Referring to FIG. 10, the multi-input OR circuit is constructed of three blocks, and each of the blocks is provided with three PMOS transistors and one NMOS transistor which are connected in series.
More specifically, PMOS transistors P11, P12, P13 and an NMOS transistor N11 are connected in series between a supply voltage terminal VD and a ground terminal G, PMOS transistors P21, P22, P23 and an NMOS transistor N12 are connected in series between a supply voltage terminal VD and a ground terminal G, and PMOS transistors P31, P32, P33 and an NMOS transistor N13 are connected in series between a supply voltage terminal VD and a ground terminal G.
Besides, the connection node OUTB between the PMOS transistors P13, P23, P33 and the respectively corresponding NMOS transistors N11, N12, N13 is connected to an output terminal OUT through an inverter Iv11.
Here, an input terminal S1 is connected to the gates of the PMOS transistor P11 at a first stage, the PMOS transistor P23 at a third stage and the PMOS transistor P32 at a second stage, an input terminal S2 is connected to the gates of the PMOS transistor P12 at the second stage, the PMOS transistor P21 at the first stage and the PMOS transistor P33 at the third stage, and an input terminal S3 is connected to the gates of the PMOS transistor P13 at the third stage, the PMOS transistor P22 at the second stage and the PMOS transistor P31 at the first stage.
When any of the input terminals S1-S3 becomes a high level, the corresponding one of the NMOS transistors N11, N12, N13 turns ON, and the corresponding ones of the PMOS transistors P11-P33 turn OFF in each individual block unit, so that the output becomes the high level.
Further, only in a case where all the input terminals S1-S3 have become a low level, all the NMOS transistors N11, N12, N13 turn OFF, and all the PMOS transistors P11-P33 of the individual blocks turn ON, so that the output becomes the low level.
Here, the threshold voltages of the PMOS transistors P11-P33 differ depending upon the stages at which these PMOS transistors P11-P33 are connected as seen from the supply voltage terminal VD, so that the delay values of the PMOS transistors P11-P33 change. The changes of the delay values become the disturbance of clock cycles called “jitter” and deteriorate a clock quality.
With the multi-input OR circuit in FIG. 10, therefore, three of the PMOS transistors P11-P33 are allotted to each of the input terminals S1-S3, and all the input terminals S1-S3 are brought to a symmetric structure, whereby delay values in the respective input terminals S1-S3 are equalized so as to suppress the jitter.
FIG. 11 is a diagram showing the second example arrangement of a multi-input OR circuit in the prior art. Incidentally, in the example of FIG. 11, a 3-input OR circuit is shown for the sake of brevity.
Referring to FIG. 11, a PMOS transistor P41, and three NMOS transistors N41, N42, N43 connected in parallel, are connected in series between a supply voltage terminal VD and a ground terminal G.
The connection nodes OUTB between the PMOS transistor P41 and the respective NMOS transistors N41, N42, N43 are connected to an output terminal OUT through an inverter IV12.
Here, an input terminal S1 is connected to the gate of the NMOS transistor N41, an input terminal S2 is connected to the gate of the NMOS transistor N42, and an input terminal S3 is connected to the gate of the NMOS transistor N43.
The gate of the PMOS transistor P41 is grounded, and a wired OR circuit in which the PMOS transistor P41 functions as a normally-ON load is constructed.
When any of the input terminals S1-S3 becomes a high level, the corresponding one of the NMOS transistors N41, N42, N43 turns ON, so that the output becomes the high level.
Further, only in a case where all the input terminals S1-S3 have become a low level, all the NMOS transistors N41, N42, N43 turn OFF, so that the output becomes the low level.
With the multi-input OR circuit in FIG. 10, however, when N input terminals exist, (N+1) transistors need to be connected in series between the supply voltage terminal VD and the ground terminal G. Therefore, as the number of input terminals increases, the number of transistors connected in series increases accordingly. This results in a problem in that the transistors fail to be rendered conductive. In accordance with a low-voltage IC process, the number of inputs of the multi-input OR circuit has been limited to 4 or so.
Meanwhile, there is also a method wherein the logical sum is taken in such a way that the multi-input OR circuit is divided into OR circuits each having a small number of inputs of 2-3 inputs, and that the OR circuits of the small number of inputs are connected in multiple stages. With this method, however, it is impossible to bring all the input terminals to a symmetric structure.
For this reason, this method has had the problem that the jitter exerts greater influence to deteriorate the clock quality.
On the other hand, with the multi-input OR circuit in FIG. 11, when any of the NMOS transistors N41, N42, N43 turns ON, a through current flows between the supply voltage terminal VD and the ground terminal G. This results in a problem in that power dissipation increases. The increase becomes more pronounced when an operating frequency heightens.
For this reason, the multi-input OR circuit in FIG. 11 is inappropriate for use in a frequency multiplier circuit in which a high-frequency operation is performed.
Therefore, one object of the present invention is to provide a pulse processing circuit which permits a low-voltage operation even in the case of an increased number of inputs, and which can take the logical sum of non-overlapping pulses with the increase of power dissipation suppressed.
Another object of the present invention is to provide a frequency multiplier circuit which permits a low-voltage operation and which can heighten a clock frequency with the increases of power dissipation and jitter suppressed.